Added CPUID based checks

Makefile

@@ -5,7 +5,7 @@ CC = ${HOME}/opt/cross/bin/i686-elf-gcc
 CPP = ${HOME}/opt/cross/bin/i686-elf-g++ 
 CFLAGS =  -ffreestanding -Og -ggdb  -Wall -Wextra
 
-OFILES =$(BUILD_DIR)/boot.o $(BUILD_DIR)/kterm.o $(BUILD_DIR)/kernel.o $(BUILD_DIR)/memory.o  $(BUILD_DIR)/paging.o	$(BUILD_DIR)/pit.o 	$(BUILD_DIR)/time.o	$(BUILD_DIR)/keyboard.o	 $(BUILD_DIR)/io.o 	$(BUILD_DIR)/gdtc.o $(BUILD_DIR)/idt.o $(BUILD_DIR)/pic.o $(BUILD_DIR)/sv-terminal.o $(BUILD_DIR)/string.o  $(BUILD_DIR)/prekernel.o $(BUILD_DIR)/cpu.o $(BUILD_DIR)/KHeap.o $(BUILD_DIR)/pci.o $(BUILD_DIR)/pcidevice.o $(BUILD_DIR)/atapiDevice.o $(BUILD_DIR)/ataDevice.o $(BUILD_DIR)/rsdp.o $(BUILD_DIR)/acpi.o 
+OFILES =$(BUILD_DIR)/boot.o $(BUILD_DIR)/kterm.o $(BUILD_DIR)/kernel.o $(BUILD_DIR)/memory.o  $(BUILD_DIR)/paging.o	$(BUILD_DIR)/pit.o 	$(BUILD_DIR)/time.o	$(BUILD_DIR)/keyboard.o	 $(BUILD_DIR)/io.o 	$(BUILD_DIR)/processor.o $(BUILD_DIR)/gdtc.o $(BUILD_DIR)/idt.o $(BUILD_DIR)/pic.o $(BUILD_DIR)/sv-terminal.o $(BUILD_DIR)/string.o  $(BUILD_DIR)/prekernel.o $(BUILD_DIR)/cpu.o $(BUILD_DIR)/KHeap.o $(BUILD_DIR)/pci.o $(BUILD_DIR)/pcidevice.o $(BUILD_DIR)/atapiDevice.o $(BUILD_DIR)/ataDevice.o $(BUILD_DIR)/rsdp.o $(BUILD_DIR)/acpi.o
 
 SRC_DIR = source
 BUILD_DIR = build
@@ -128,6 +128,8 @@ $(BUILD_DIR)/prekernel.o:
 $(BUILD_DIR)/cpu.o:
 	$(CPP) -c $(SRC_DIR)/kernel/cpu.cpp -o $(BUILD_DIR)/cpu.o $(CFLAGS) -fno-exceptions -fno-rtti
 
+$(BUILD_DIR)/processor.o:
+	$(CPP) -c $(SRC_DIR)/kernel/i386/processor.cpp -o $(BUILD_DIR)/processor.o $(CFLAGS) -fno-exceptions -fno-rtti
 
 
 # Assembly -> Object files

source/kernel/i386/README.md

@@ -0,0 +1,2 @@
+# architecture specific implementations 
+## This will contain I386 Architecture specific implementations

source/kernel/i386/processor.cpp

@@ -0,0 +1,73 @@
+//
+// Created by nigel on 17/02/23.
+//
+
+#include "processor.h"
+
+
+uint32_t processor::cap_page;
+uint32_t processor::cap_page1;
+uint32_t processor::cap_page7 ;
+
+void processor::initialize()
+{
+
+    asm volatile ("movl $0x80000001, %%eax;"
+                  "CPUID;"
+                  "movl %%edx, %0"
+                  :: "m"(cap_page));
+
+    asm volatile ("movl $0x01, %%eax; "
+                  "CPUID;"
+                  "movl %%edx, %0"
+                  :: "m"(cap_page1));
+
+    asm volatile ("movl $0x07, %%eax;"
+                  "movl $0x0, %%ecx;"
+                  "CPUID;"
+                  "movl %%edx, %0"
+                  :: "m"(cap_page7));
+
+}
+
+bool processor::hasAMXExtension()
+{
+    return (cap_page7 & AMX_TYPE::AMX_BF16) || (cap_page7 & AMX_TYPE::AMX_TILE) || (cap_page7 & AMX_TYPE::AMX_INT8);
+}
+
+
+/*
+ * PSE: page-size extensions for 32-bit paging.
+ * If CPUID.01H:EDX.PSE [bit 3] = 1, CR4.PSE may be set to 1, enabling support for 4-MByte pages with 32-bit paging
+ */
+bool processor::has32bitPagingSupport() {
+    // is the PSE bit set
+    return cap_page1 & (0x1 << 3);
+}
+
+/*
+ * PAE: physical-address extension.
+ * If CPUID.01H:EDX.PAE [bit 6] = 1, CR4.PAE may be set to 1, enabling PAE paging (this setting is also required
+ * for 4-level paging and 5-level paging).
+ */
+bool processor::hasPAEExtension(){
+    return cap_page1 & (0x1 << 6);
+}
+
+/*
+ * PGE: global-page support.
+ * If CPUID.01H:EDX.PGE [bit 13] = 1, CR4.PGE may be set to 1, enabling the global-page feature (see Section
+ * 4.10.2.4).
+ */
+bool processor::hasPageSupport(){
+    return cap_page1 & (0x1 << 13);
+}
+
+/*
+ * Page1GB: 1-GByte pages.
+ * If CPUID.80000001H:EDX.Page1GB [bit 26] = 1, 1-GByte pages may be supported with 4-level paging and 5-
+ * level paging (see Section 4.5).
+ */
+bool processor::gigabytePages() {
+    return cap_page & (0x1 << 26);
+}

source/kernel/i386/processor.h

@@ -0,0 +1,29 @@
+//
+// Created by nigel on 17/02/23.
+//
+#pragma  once
+#include "../terminal/kterm.h"
+class processor {
+public:
+    static void initialize();
+
+    // Based on information from https://en.wikichip.org/wiki/x86/amx#Detection
+    enum  AMX_TYPE{
+        AMX_BF16 = (0x1 << 22),
+        AMX_TILE = (0x1 << 24),
+        AMX_INT8 = (0x1 << 25)
+    };
+    static bool hasAMXExtension();
+    static bool has32bitPagingSupport();
+    static bool hasPageSupport();
+    static bool gigabytePages();
+
+    static bool hasPAEExtension();
+
+private:
+    static uint32_t cap_page;
+    static uint32_t cap_page1;
+    static uint32_t cap_page7;
+
+
+};

source/kernel/kernel.cpp

@@ -10,19 +10,20 @@ extern "C"{
 #include "memory/gdt/gdtc.h"
 #include "memory/TaskStateSegment.h"
 #include "supervisorterminal/superVisorTerminal.h"
-
 #include "drivers/vga/VBE.h"
 #include "drivers/pci/pci.h"
 #include "drivers/pit/pit.h"
 #include "drivers/acpi/acpi.h"
 #include "drivers/ide/ide.h"
-
+#include "i386/processor.h"
 #include "terminal/kterm.h"
 #include "interrupts/idt.h"
 #include "serial.h"
+
 extern "C"  void LoadGlobalDescriptorTable();
 extern "C" void jump_usermode();
 
+
 void set_protected_bit()
 {
     // Set the protected bit of control register 0
@@ -57,10 +58,13 @@ extern "C" void kernel ()
 
     pit_initialise();
 
-    ACPI::initialize();
+    // ACPI::initialize();
     PCI::Scan();
 
-    TestIDEController();
+    //TestIDEController();
+
+
+    processor::initialize();
 
     printf("Enable Protected mode and jump to kernel main\n");
 

source/kernel/supervisorterminal/superVisorTerminal.cpp

@@ -91,7 +91,8 @@ extern "C" void startSuperVisorTerminal()
                 };
 
 
-                
+                // FIXME: If no drive is connected we continue trying to read from
+                // a not connected drive! 
                 ATA_DEVICE::Identify((uint16_t) BUS_PORT::Primary, DEVICE_DRIVE::MASTER);
 
                 const int C = 0;