73 lines
1.8 KiB
C++
73 lines
1.8 KiB
C++
//
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// Created by nigel on 17/02/23.
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//
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#include "processor.h"
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uint32_t processor::cap_page;
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uint32_t processor::cap_page1;
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uint32_t processor::cap_page7 ;
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void processor::initialize()
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{
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asm volatile ("movl $0x80000001, %%eax;"
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"CPUID;"
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"movl %%edx, %0"
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:: "m"(cap_page));
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asm volatile ("movl $0x01, %%eax; "
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"CPUID;"
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"movl %%edx, %0"
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:: "m"(cap_page1));
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asm volatile ("movl $0x07, %%eax;"
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"movl $0x0, %%ecx;"
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"CPUID;"
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"movl %%edx, %0"
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:: "m"(cap_page7));
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}
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bool processor::hasAMXExtension()
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{
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return (cap_page7 & AMX_TYPE::AMX_BF16) || (cap_page7 & AMX_TYPE::AMX_TILE) || (cap_page7 & AMX_TYPE::AMX_INT8);
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}
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/*
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* PSE: page-size extensions for 32-bit paging.
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* If CPUID.01H:EDX.PSE [bit 3] = 1, CR4.PSE may be set to 1, enabling support for 4-MByte pages with 32-bit paging
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*/
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bool processor::has32bitPagingSupport() {
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// is the PSE bit set
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return cap_page1 & (0x1 << 3);
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}
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/*
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* PAE: physical-address extension.
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* If CPUID.01H:EDX.PAE [bit 6] = 1, CR4.PAE may be set to 1, enabling PAE paging (this setting is also required
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* for 4-level paging and 5-level paging).
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*/
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bool processor::hasPAEExtension(){
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return cap_page1 & (0x1 << 6);
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}
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/*
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* PGE: global-page support.
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* If CPUID.01H:EDX.PGE [bit 13] = 1, CR4.PGE may be set to 1, enabling the global-page feature (see Section
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* 4.10.2.4).
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*/
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bool processor::hasPageSupport(){
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return cap_page1 & (0x1 << 13);
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}
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/*
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* Page1GB: 1-GByte pages.
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* If CPUID.80000001H:EDX.Page1GB [bit 26] = 1, 1-GByte pages may be supported with 4-level paging and 5-
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* level paging (see Section 4.5).
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*/
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bool processor::gigabytePages() {
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return cap_page & (0x1 << 26);
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} |