2022-09-01 15:02:04 +00:00
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#pragma once
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#include <stdint.h>
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2022-08-16 17:06:16 +00:00
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/*
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Based on Intel specifications.
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C++ interface for the cpu.s assembly file.
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©Nigel Barink - 2022
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*/
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/*
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* EFLAGS FUNCTIONS
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*/
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2022-09-01 18:16:16 +00:00
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uint32_t GetEFLAGS();
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2022-08-16 17:06:16 +00:00
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/*
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* CONTROL_REGISTER_0 FUNCTIONS
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*/
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2022-09-01 18:16:16 +00:00
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uint32_t GetCR0();
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2022-08-16 17:06:16 +00:00
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/*
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struct CR0_Register {
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uint8_t PE :1; // Protection Mode Enabled 0
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uint8_t MP :1; // Monitor co-processor 1
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uint8_t EM :1; // Emulation 2
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uint8_t TS :1; // Task switched 3
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uint8_t ET :1; // Extension Type 4
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uint8_t NE :1; // Numeric error 5
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uint16_t Reserved :10; // 6,7,8,9,10,11,12,13,14,15
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uint8_t WP :1; // Write Protect 16
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uint8_t Reserved :1; // 17
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uint8_t AM :1; // Alligment Task 18
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uint16_t Reserved :10; // 19,20,21,22,23,24,25,26,27,28
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uint8_t NW :1; // Not-write through 29
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uint8_t CD :1; // Cache disable 30
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uint8_t PG :1; // Paging 31
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};*/
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#define GET_PE_BIT(CONTROL_REGISTER_0) (CONTROL_REGISTER_0&0x1)
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#define GET_MP_BIT(CONTROL_REGISTER_0) (CONTROL_REGISTER_0&0x2)
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#define GET_EM_BIT(CONTROL_REGISTER_0) (CONTROL_REGISTER_0&0x3)
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#define GET_TS_BIT(CONTROL_REGISTER_0) (CONTROL_REGISTER_0&0x4)
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#define GET_ET_BIT(CONTROL_REGISTER_0) (CONTROL_REGISTER_0&0x5)
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#define GET_NE_BIT(CONTROL_REGISTER_0) (CONTROL_REGISTER_0&0x6)
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2022-08-17 12:17:58 +00:00
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#define GET_PG_BIT(CONTROL_REGISTER_0) (CONTROL_REGISTER_0>>31)
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/*
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* CONTROL_REGISTER_4 FUNCTIONS
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*/
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2022-09-01 18:16:16 +00:00
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uint32_t GetCR4();
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2022-08-17 12:17:58 +00:00
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#define GET_PSE_BIT(CONTROL_REGISTER_4) (CONTROL_REGISTER_4&0x4)
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#define GET_PAE_BIT(CONTROL_REGISTER_4) (CONTROL_REGISTER_4&0x5)
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2022-08-18 22:44:52 +00:00
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/*
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* CONTROL_REGISTER_2 FUNCTIONS
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*/
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2022-09-01 18:16:16 +00:00
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uint32_t GetCR2();
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2022-08-18 22:44:52 +00:00
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/*
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* CONTROL_REGISTER_3 FUNCTIONS
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*/
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2022-09-01 18:16:16 +00:00
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uint32_t GetCR3();
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